1. Field of the Invention
The present invention relates to a cache memory control circuit and method in which a cache access is accepted to read or write a piece of cache data from/in a cache memory during an external access resulting from a cache miss-hit.
2. Description of the Prior Art
2.1. Previously Proposed Art
As an example of a conventional cache memory control circuit, a cache bypass buffer which is, for example, disclosed in detail in "Computer System Engineering" Oct. 14, 1988 (pp. 97-98) written by S. Tomira and K. Murakami and published by Syoukoudo has been known.
FIG. 1 is a flow chart showing an example of an operation performed in the conventional cache memory control circuit.
In cases where a cache address in which a piece of cache data to be read out or written is stored does not exist in a cache memory, a miss-hit occurs when the cache memory is accessed to read out or write a piece of cache data from/in the cache address of the cache memory. As shown in FIG. 1, when a miss-hit occurs at a first clock T1 in a reading cache access because a cache address in which a piece of cache data to be read out is stored does not exist in a cache memory, an external access is performed to read a piece of external data stored in a corresponding address of an external memory such as another cache memory or an external main memory. After the external access is successfully finished at a fifth clock T5, a next reading cache access is performed at a sixth clock T6. Therefore, a next cache access is undesirably delayed until an external access relating to a miss-hit is finished.
To enhance the performance of the cache memory, it is required to accept the next cache access during the external access relating to the miss-hit. In cases where a reading operation is performed as a next cache access to read a piece of required data stored in a remarked address before an external access performed to obtain the required data from an external memory is finished, the required data cannot be read out from the remarked address in the next cache access. Therefore, it is necessary to delay the performance of the next cache access until the external access is finished. In contrast, in cases where a writing operation is performed as a next cache access, the writing operation can be fundamentally performed before the finish of an external access.
2.2. Problems to be Solved by the Invention
However, there is a probability that a piece of external data is written in a remarked address after the writing operation as the next cache access is performed to write a piece of updated data in the remarked address. Therefore, there is a drawback that a piece of updated data relating to the next cache access is replaced with a piece of previous data relating to the external data to destroy the updated data.